Low-Power Double-Edge Triggered D Flip-Flop Based on the Conditional Discharge Technique

Abstract

In this paper, a high speed and low power double-edge triggered D flip-flop based on conditional discharge technique is proposed. By applying a scheme in the conditional discharge path, which takes the voltage difference between the internal node and the output node as the conduction condition, the circuit not only improves the circuit structure, but also reduces the power dissipation and the total power delay product. The simulation results show that the proposed D flip-flop has the correct logic function and is superior to other literatures in terms of power dissipation, delay and cost at the working frequency of 250MHz.