Evaluation of Cache Compression for Elbrus Processors

Abstract

Data compression in cache memory allows increasing the effective capacity, which improves the hit rate and only insignificantly affects power consumption and die area. In this paper, the results of the first research on cache compression in processors with Elbrus architecture are presented. Base+Delta (B+Δ) and Base-Delta-Immediate (BΔI) compression algorithms are selected for hardware implementation for their high efficiency and lower decompression latency compared to other algorithms. The modified versions of these algorithms, B+Δ* and BΔI*, which allow to reduce implementation complexity and further shorten the latency, are presented. Additionally, a new set of compression schemes for modified algorithms (labeled as BΔI*-HL algorithm) is proposed to account for width of the interfaces and internal data buses. The algorithms were implemented using Verilog HDL and evaluated on FPGA prototype of Elbrus-8C2 processor and SPEC CPU2000 benchmark suite. The results show that BΔI* demonstrates almost equal of greater compression ration as the original BÄI algorithm while has significantly lower implementation complexity. The algorithm BΔI*-HL is proposed as the most suitable for hardware implementation with average compressed lines share of 24.4% and mean compression ratio of 1.246.