On Bit-Serial NoCs for FPGAs

Abstract

We can build lightweight bit-serial FPGA NoC routers thatcost 20 LUT, 17 FF per router and operate at 800–900 MHzspeeds. Each bit-serial router implements deflection-routing on aunidirectional torus topology requiring 1b-wide connection perport. The key ideas that enable this implementation are (1)reformulation of the dimension-ordered routing (DOR) functionusing compact 1 LUT, 1 FF streaming pattern matchers, (2)compact retiming of the datapath signals into SRL16 blocks, and(3) careful FPGA layout to efficiently pack the router logic intosmall rectangular regions 2×4 SLICEs on the chip. We anticipatethese bit-serial NoCs can be used in a variety of scenariosincluding overlay support for triggered debug, lightweight controlsignal dissemination, massively-parallel bit-serial processing.