Heterogeneous NoC Physical-Level Low-Power Implementation

Abstract

A heterogeneous network-on-chip (NoC) is presented and implemented focusing on low-power communication in various design levels such as circuits, signaling, channel coding for possible application to energy-efficient NoC design. It incorporates heterogeneous intellectual properties (IPs) interconnected in a hierarchical star topology, and provides integrated IPs, which operate at different clock frequencies, with packet-switched serial- communication infrastructure. Physical level-oriented low-power implementation is devised, and applied to achieve the power-efficient on-chip communications.