Hardware design and arithmetic algorithms for a variable-precision, interval arithmetic coprocessor

M. Schulte, E. Swartzlander
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引用次数: 40

Abstract

This paper presents the hardware design and arithmetic algorithms for a coprocessor that performs variable-precision, interval arithmetic. The coprocessor gives the programmer the ability to specify the precision of the computation, determine the accuracy of the result, and recompute inaccurate results with higher precision. Direct hardware support and efficient algorithms for variable-precision, interval arithmetic greatly improve the speed, accuracy, and reliability of numerical computations. Performance estimates indicate that the coprocessor is 200 to 1,000 times faster than a software package for variable-precision, interval arithmetic. The coprocessor can be implemented on a single chip with a cycle time that is comparable to IEEE double-precision floating point coprocessors.<>
可变精度区间算术协处理器的硬件设计和算法
本文介绍了一种可实现变精度区间运算的协处理器的硬件设计和算法。协处理器使程序员能够指定计算的精度,确定结果的精度,并以更高的精度重新计算不准确的结果。直接的硬件支持和有效的变精度、区间算法大大提高了数值计算的速度、精度和可靠性。性能估计表明,协处理器比用于变精度区间算法的软件包快200到1000倍。该协处理器可以在单个芯片上实现,其周期时间与IEEE双精度浮点协处理器相当。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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