A 6.38 fJ/conversion 0.6V 0.43μW 100 kS/s 10-bit successive approximation ADC

Abstract

This work presents a 10-bit successive approximation ADC for low voltage and low power applications. The chip operating voltage is 0.6 V with single-ended rail-to-rail swing input signal. Binary-weighted multilayer sandwich capacitor array is used in the digital to analog converter employed in the ADC to reduce the overall capacitance value and power consumption effectively. The proposed ADC is designed with 0.18 μm CMOS process. The simulation results at 0.6 V supply voltage, 100 kS/s sampling rate, and 1.38 kHz rail-to-rail swing input, an SNDR of 60.4 dB is achieved with 0.43 μW power consumption. The FOM is 6.38 fJ per conversion step.