Sequential design of a 8192 complex point FFT in OFDM receiver

Se Ho Park, Dong Hwan Kim, D. Han, Kyu Lee, S. Park, J. Choi
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引用次数: 10

Abstract

In this paper we propose an implementation method for a single-chip 8192 complex point FFT in terms of sequential data processing. In order to reduce the required chip area for the sequential processing of 8 K complex data, a DRAM-like pipelined commutator architecture is used. The 16-point FFT is a basic building block of the entire FFT chip, and the 8192-point FFT consists of the cascaded blocks with six stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding. As a result the proposed structure brings about the 55% chip size reduction compared with conventional approach.
OFDM接收机中8192复点FFT的顺序设计
本文从顺序数据处理的角度提出了一种8192单片机复点FFT的实现方法。为了减少顺序处理8k复杂数据所需的芯片面积,采用了类似dram的流水线换向器结构。16点FFT是整个FFT芯片的基本构建块,而8192点FFT由具有6级基数4和1级基数2的级联块组成。由于每个阶段都需要在保持适当信噪比的同时对结果位进行舍入,因此使用收敛块浮点(CBFP)算法进行有效的内部位舍入。因此,与传统方法相比,所提出的结构使芯片尺寸减小55%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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