Encapsulation of Full Adder Using 180nm CNTFET

Abstract

Binary logic is limited to only two states as it is two-valued logic. The ternary logic is the promising alternative to the conventional binary logic which is also called as trivalent logic. Energy efficiency and reduction in chip area as well as complexity plays an important role in ternary. Nowadays CNTFET device is more significant than the other due to higher channel mobility and also enhanced the gate capacitance. In CMOS, the complexity of an interconnect and chip area is increased as the number of function increases. This paper proposed an approach of using CNTFETs operate for faster and even consume less power in comparison with traditional MOS devices. Ternary full adder is designed using ternary decoder and result is simulated in TSPICE.