Modeling and Simulation of 7T SRAM Cell at Various Process Corners at 45 nm Process Technology

Abstract

Designing static random access memory cell (SRAM), low power and leakage current using nano-scale technology ranges, Low power supply voltage is an effective technique for low power reduction in memory design, however traditional memory cell design fails to operate at ultra low voltage regime, then a new cell structure need to operate cell in low voltage regime. Therefore a single ended input output 7 transistor SRAM cell for using 45nm cmos technology and it is suitable for low voltage regime. Schmitt trigger based SRAM is proposed which provide better read stability, write ability and process variation tolerance compared to standard 6 transistor SRAM cell. This technology reduces power as well leakage current and improves signal noise margin (SNM).