Optimised Hardware Implementation of AES for Improving Energy Efficiency of Low-Power Devices

Abstract

Most commercial ultra-low power microcontrollers available in the market have inbuilt circuitry for crypto operations, radio for transmission and multiple sleep modes. Sleep modes put the processor into sleep mode while using integrated peripherals, thereby saving the power and battery life of the constrained devices. The add-on circuitry in the microcontrollers has promised higher security at extremely low power by optimising the sleep modes using low-level programming. Dedicated hardware blocks carry out most encryption techniques within the processor for energy, time, and memory efficiency. This necessitates the power optimisation in embedded applications to be an integral part of the development process for overall efficiency, as it is essential to understand how crypto accelerators, software algorithms, and power-saving modes work together. In this work, different optimisation techniques have been adopted to enhance the power consumption of EFM32PG12, an IoT hardware platform developed by Silicon Labs, using sleep modes and the hardware accelerator of the board. The sleep modes have been utilised in the AES encryption algorithm to reduce the overall power consumption on a hardware mote. The combination of the hardware accelerator and the sleep modes significantly improved the performance and reduced the power consumption of AES encryption and decryption on the hardware platform.