{"title":"Off-current characteristics of conductivity modulated TFT","authors":"K.P. Anish Kumar, J. Sin","doi":"10.1109/TENCON.1995.496333","DOIUrl":null,"url":null,"abstract":"This paper reports the leakage current characteristics of Conductivity Modulated Thin Film Transistor (CMTFT) fabricated using polycrystalline silicon. The transistor uses the idea of conductivity modulation in the offset region to obtain a significant reduction in on-state resistance. Experimental on-state and off-state current-voltage characteristics of the CMTFT have been compared with those of the conventional offset drain device. The devices were fabricated using a low temperature process (620/spl deg/C) which is highly desirable for large area electronic applications.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"20 2","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TENCON.1995.496333","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper reports the leakage current characteristics of Conductivity Modulated Thin Film Transistor (CMTFT) fabricated using polycrystalline silicon. The transistor uses the idea of conductivity modulation in the offset region to obtain a significant reduction in on-state resistance. Experimental on-state and off-state current-voltage characteristics of the CMTFT have been compared with those of the conventional offset drain device. The devices were fabricated using a low temperature process (620/spl deg/C) which is highly desirable for large area electronic applications.