A fast capability extension to a RISC architecture

Abstract

The concept of capability-based addressing originated in the 60's a means of promoting security and information sharing in computer systems; however, poor performance of early capability-based machines prevented it from becoming widespread. We describe a capability-based architecture implemented as a fairly straightforward extension of a conventional RISC architecture. Without compromising the security aspect, the capability mechanism was simplified to allow for an implementation that does not stretch the cycle time of the core architecture. Simulated executions of benchmark programs show that the performance penalty of using the capability mechanism is in the range of 16% to 19%, an acceptable price to pay for security. The proposed architecture can thus be a viable solution for meeting the increased demands for security as information sharing becomes pervasive.