High performance multiplier-less pipelined FPGA architecture for 2-D non-separable quaternionic filter banks

Abstract

This paper presents a systematic design of the 2-D non-separable quaternionic paraunitary filter banks $(Q -$PUFB) based on the integer-to-integer invertible quaternionic multiplier applied to image processing. In order to achieve higher transform coding gains in multidimensional domain with relatively low-complexity implementation, orthogonal transform 8-channel $Q -$PUFB factorize into two-dimensional non-separable structures called ”64in-64out” (2D NS $Q -$PUFB). The given structures can be mapped directly to parallel-pipelined processor architecture with minimal latency time $4 (N +1)$ quaternion multiplication operations, where N is transform order of $Q -$PUFB. The latency of parallel-pipelined processing does not depend on the size of the original image. Experimental design results on resource utilization and total throughput are obtained using a Xilinx Ultrascale + FPGA Series. System prototype total throughput variates from 13.8 up to 55 million pixels per second and depends on fixed point constraints.