{"title":"Automatic package and board decoupling capacitor placement using genetic algorithms and M-FDM","authors":"K. Bharath, E. Engin, M. Swaminathan","doi":"10.1145/1391469.1391611","DOIUrl":null,"url":null,"abstract":"In the design of complex power distribution networks (PDN) with multiple power islands, it is required that the PDN represents a low impedance as seen by the digital modules. This is to reduce the simultaneous switching noise (SSN), generated due to the switching activity of digital drivers. Typically this reduction in impedance is accomplished by placing decoupling capacitors between the power and ground planes of a package or board. However, the performance of the decoupling solution is a function of capacitor selection and its placement. In this paper, an automatic capacitor placement optimization method has been proposed. This method relies on a genetic algorithm to provide a stochastic search of the design space, while employing an efficient core PDN simulator based on the multi-layer finite difference method (M-FDM). The technique has been employed to show optimized placements for split planes as well as for a realistic multi-layer server board.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"24","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 45th ACM/IEEE Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1391469.1391611","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 24
Abstract
In the design of complex power distribution networks (PDN) with multiple power islands, it is required that the PDN represents a low impedance as seen by the digital modules. This is to reduce the simultaneous switching noise (SSN), generated due to the switching activity of digital drivers. Typically this reduction in impedance is accomplished by placing decoupling capacitors between the power and ground planes of a package or board. However, the performance of the decoupling solution is a function of capacitor selection and its placement. In this paper, an automatic capacitor placement optimization method has been proposed. This method relies on a genetic algorithm to provide a stochastic search of the design space, while employing an efficient core PDN simulator based on the multi-layer finite difference method (M-FDM). The technique has been employed to show optimized placements for split planes as well as for a realistic multi-layer server board.