Hardware implementation of maximum Lyapunov exponent

Abstract

In this paper a hardware implementation of a Maximum Lyapunov Exponent (MLE) quantifier is designed and implemented using a field programmable gate array (FPGA). The design was optimized in terms of accuracy employing floating point architecture to represent the values. The proposed design takes advantage of the underline parallelism of the MLE computation equations and allows its concurrent implementation based on FPGA technology.