Maximum Error-Aware Design of Approximate Array Multipliers

Abstract

Approximate computing is considered as a processing approach to design of area-, power- or performance-efficient circuits. Approaches to approximate computing are to replace an exact arithmetic circuit with an approximate circuit. In this paper, we propose a methodology to systematically design a series of approximate array multipliers with different accuracy, area, power and delay. A circuit designer can select the one which satisfies the requirement on accuracy. Experimental results show the effectiveness of our approximate multipliers against existing approximate multipliers.