An enhanced DLX-based superscalar system simulator

Abstract

We have designed a DLX-based superscalar processor simulator. This simulator provides many more functions than its predecessors developed elsewhere. We have added trap handlers and required C functions in the system so that most of the SPEC92 programs now run on the simulator. In addition, this simulator is fully configurable and re-configurable. Specifically, the following options and functions are provided by the simulator. • Central window versus distributed reservation stations. • Branch prediction mechanisms using static or dynamic schemes. The later provides branch target buffer and branch history table. • Configurable functional units. • A fully configurable KNL non-blocking cache structure incorporated int he simulator. (K: the number of ways. N: the number of cache lines in a way. L: line size). Split versus unified option and cm + βmL/D memory latency model. • Better debugging functions allowing the interruption of the simulation, reconfiguration, restart in a cycle-by-cycle fashion, or run to the end. • NT/Win95 platform ready. This DLX-based superscalar simulator is instruction-driven, which offers richer educational features than most of the trace-driven simulators. For information about this simulator, please refer to http://com.el.yuntech.edu.tw.