A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference

Abstract

This paper presents an SRAM-based analog Compute-in-Memory (CiM) macro in 22 nm CMOS process. By introducing a C-2C capacitor ladder-based charge domain computing scheme, the CiM prototype chip demonstrates 2k multiply-accumulation (MAC) operations in one clock cycle and achieves 32.2 TOPS/W peak energy efficiency and 4.0 TOPS/mm2 peak area efficiency with 8-bit precision in both input activation and weight. A variety of analog impairment factors were analyzed during the testchip implementation to ensure sufficiently high multibit linearity.