A 100-MHz 256b-I/O 1-Mb planar nonvolatile STT-MRAM with novel memory cells

Rui Wang, H. Dery, Michael C. Huang, Hui Wu
{"title":"A 100-MHz 256b-I/O 1-Mb planar nonvolatile STT-MRAM with novel memory cells","authors":"Rui Wang, H. Dery, Michael C. Huang, Hui Wu","doi":"10.1109/NVMTS.2016.7781511","DOIUrl":null,"url":null,"abstract":"This paper presents a 1Mb STT-MRAM consisting of novel planar memory cells with built-in differential voltage output. Each memory cell contains four planar ferromagnets, one PMOS and one NMOS to enable read operation, one NMOS to enable write operation and four transmission gates to pass write current in opposite directions. The output differential voltage of two read contacts in each memory cell is 23.66 mV for logic '1' and only 0.46 mV for logic '0', which renders high signal-to-noise ratio. Estimated area of each memory cell in 65-nm CMOS technology is 1.5 um2 (355 F2). The proposed 1Mb STT-MRAM consumes dynamic write power of 12.8 mW, static leakage power of 4mW and dynamic read power of 11.10 mW to achieve 100MHz operation.","PeriodicalId":228005,"journal":{"name":"2016 16th Non-Volatile Memory Technology Symposium (NVMTS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 16th Non-Volatile Memory Technology Symposium (NVMTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NVMTS.2016.7781511","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

This paper presents a 1Mb STT-MRAM consisting of novel planar memory cells with built-in differential voltage output. Each memory cell contains four planar ferromagnets, one PMOS and one NMOS to enable read operation, one NMOS to enable write operation and four transmission gates to pass write current in opposite directions. The output differential voltage of two read contacts in each memory cell is 23.66 mV for logic '1' and only 0.46 mV for logic '0', which renders high signal-to-noise ratio. Estimated area of each memory cell in 65-nm CMOS technology is 1.5 um2 (355 F2). The proposed 1Mb STT-MRAM consumes dynamic write power of 12.8 mW, static leakage power of 4mW and dynamic read power of 11.10 mW to achieve 100MHz operation.
具有新颖存储单元的100 mhz 256b-I/O 1 mb平面非易失性STT-MRAM
本文提出了一种由内置差分电压输出的新型平面存储单元组成的1Mb STT-MRAM。每个存储单元包含四个平面铁磁体、一个PMOS和一个NMOS,一个NMOS使能读取操作、一个NMOS使能写入操作和四个传输门,以通过相反方向的写入电流。每个存储单元的两个读触点输出差分电压,逻辑“1”为23.66 mV,逻辑“0”仅为0.46 mV,信噪比高。65nm CMOS技术中每个存储单元的估计面积为1.5 um2 (355 F2)。本文提出的1Mb STT-MRAM实现100MHz工作所需的动态写功率为12.8 mW,静态漏功率为4mW,动态读功率为11.10 mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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