Optimization issues for fully-integrated CMOS DC-DC converters

Abstract

A general approach is given for minimizing the chip area occupied by fully integrated CMOS continuous mode buck and boost converters. It is shown that most significant portion of the area is occupied by the planar inductors. It is also shown that in most cases, continuous conduction mode requires that the minimum (critical) inductance must be used to minimize area. A design example accompanies the analysis, along with experimental results from a test integrated circuit.