Y. Nakahara, T. Fukai, M. Togo, S. Koyama, H. Morikuni, T. Matsuda, K. Sakamoto, A. Mineji, S. Fujiwara, Y. Kunimune, M. Nagase, T. Tamura, N. Onoda, S. Miyake, Y. Yama, T. Kudoh, M. Ikeda, Y. Yamagata, T. Yamamoto, K. Imai
{"title":"A robust 65-nm node CMOS technology for wide-range Vdd operation","authors":"Y. Nakahara, T. Fukai, M. Togo, S. Koyama, H. Morikuni, T. Matsuda, K. Sakamoto, A. Mineji, S. Fujiwara, Y. Kunimune, M. Nagase, T. Tamura, N. Onoda, S. Miyake, Y. Yama, T. Kudoh, M. Ikeda, Y. Yamagata, T. Yamamoto, K. Imai","doi":"10.1109/IEDM.2003.1269279","DOIUrl":null,"url":null,"abstract":"We have developed a highly reliable 65 nm node CMOS technology, enabling a wide-range of Vdd operation, including overdrive mode. Process conditions are carefully optimized from the various aspects of device reliability and performance. We have utilized an oxynitride gate, arsenic-assisted phosphorus S/D ion-implantation, Ni-silicidation, stress controlled SiN layer process, and an offset-spacer process in order to improve the drive-current at low voltage operation and reliability at high voltage operation. The obtained drive-currents are 730/310 /spl mu/A//spl mu/m with an off-current of 80 nA//spl mu/m at a standard supply voltage of 0.9 V, and 1150/550 /spl mu/A//spl mu/m with an off-current of 180 nA//spl mu/m at an overdrive voltage of 1.2 V, while satisfying strict criteria for transistor reliability.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"327 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Electron Devices Meeting 2003","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2003.1269279","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
We have developed a highly reliable 65 nm node CMOS technology, enabling a wide-range of Vdd operation, including overdrive mode. Process conditions are carefully optimized from the various aspects of device reliability and performance. We have utilized an oxynitride gate, arsenic-assisted phosphorus S/D ion-implantation, Ni-silicidation, stress controlled SiN layer process, and an offset-spacer process in order to improve the drive-current at low voltage operation and reliability at high voltage operation. The obtained drive-currents are 730/310 /spl mu/A//spl mu/m with an off-current of 80 nA//spl mu/m at a standard supply voltage of 0.9 V, and 1150/550 /spl mu/A//spl mu/m with an off-current of 180 nA//spl mu/m at an overdrive voltage of 1.2 V, while satisfying strict criteria for transistor reliability.
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