Controllable Arbitrary Integer Frequency Divider Based on VHDL

H. Tian, Shuo Shi, Jun Zhang, Hong-Dong Zhao
{"title":"Controllable Arbitrary Integer Frequency Divider Based on VHDL","authors":"H. Tian, Shuo Shi, Jun Zhang, Hong-Dong Zhao","doi":"10.1109/JCAI.2009.62","DOIUrl":null,"url":null,"abstract":"The key technique for the design of a frequency divider is to find a function between the input and output. In general, the design process and circuit of a frequency divider is complicated, modification and transplantation for it is difficult. A creative design method of CAIFD (Controllable Arbitrary Integer Frequency Divider) is presented in this paper, which uses the VHDL (VHSIC Hardware Description Language ) source code to synthesize a FPGA (Field Programmable Gate Array) or a CPLD (Complex Programmable Logic Device) circuit that produces a 50% duty cycle n (n is a integer and n≫0 ) controllable waveform. In order to validate the design method, CAIFD which has different frequency coefficients is simulated in device of ALTERA Corporation's EP2S15F484C3. Results of the experiment shows that modification and transplantation of CAIFD is easy, moreover the performance is steady and reliable.","PeriodicalId":154425,"journal":{"name":"2009 International Joint Conference on Artificial Intelligence","volume":"242 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Joint Conference on Artificial Intelligence","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/JCAI.2009.62","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

The key technique for the design of a frequency divider is to find a function between the input and output. In general, the design process and circuit of a frequency divider is complicated, modification and transplantation for it is difficult. A creative design method of CAIFD (Controllable Arbitrary Integer Frequency Divider) is presented in this paper, which uses the VHDL (VHSIC Hardware Description Language ) source code to synthesize a FPGA (Field Programmable Gate Array) or a CPLD (Complex Programmable Logic Device) circuit that produces a 50% duty cycle n (n is a integer and n≫0 ) controllable waveform. In order to validate the design method, CAIFD which has different frequency coefficients is simulated in device of ALTERA Corporation's EP2S15F484C3. Results of the experiment shows that modification and transplantation of CAIFD is easy, moreover the performance is steady and reliable.
基于VHDL的可控任意整数分频器
分频器设计的关键技术是在输入和输出之间找到一个函数。一般来说,分频器的设计过程和电路比较复杂,修改和移植比较困难。本文提出了一种新颖的可控任意整数分频器(CAIFD)的设计方法,利用VHSIC硬件描述语言(Hardware Description Language, VHDL)源代码合成FPGA (Field Programmable Gate Array,现场可编程门阵列)或CPLD (Complex Programmable Logic Device,复杂可编程逻辑器件)电路,产生50%占空比n (n为整数,n比0)的可控波形。为了验证设计方法,在ALTERA公司的EP2S15F484C3器件上对具有不同频率系数的CAIFD进行了仿真。实验结果表明,该系统易于修改和移植,且性能稳定可靠。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信