Easily testable PLA-based finite state machines

Abstract

A synthesis procedure, which begins with a state transition graph description of a sequential machine and produces an optimized, easily testable PLA (programmable logic array) based logic implementation, is outlined. A procedure is proposed for constrained state assignment and logic optimization that guarantee testability for all combinationally irredundant crosspoint faults in a PLA-based finite-state machine. No direct access to the flip-flops is required. The test sequences to detect these faults can be obtained using combinational test generation techniques alone. This procedure thus represents an alternative to a scan design methodology. Results are presented to illustrate the efficacy of this procedure. The area/performance penalties in return for easy testability are small.<>