Design of Low power and Area Efficient 8-bit ALU using GDI

Abstract

The design of an 8-bit Arithmetic Logic Unit (ALU) by using four different techniques which are conventional CMOS technique, Sleepy Transistor technique, LECTOR technique and Forced Stack technique. ALU is the most crucial and core component of central processing unit as well as of numbers of embedded system and microprocessors. In this work, ALU consists of 4x1 multiplexer and 2x1 multiplexer and full adder designed to implement Logical operations such as AND, OR, XOR, NOT and Arithmetic operations such ADD WITH CARRY, SUBTRACT WITH BORROW, ADD WITHOUT CARRY, SUBTRACT WITHOUT BORROW. The low power techniques are becoming more important due to rapid development of portable digital applications, demand for high-speed and low power consumption. GDI (Gate Diffusion Input) is one of the low power and area efficient technique. GDI requires less number of transistors compared to CMOS technology. Arithmetic logic unit (ALU) is an important part of microprocessor. In digital processor logical and arithmetic operation executes using ALU. In this paper we describes 8-bit ALU using low power11-transistor full adder (FA) and Gate diffusion input (GDI) based multiplexer. By using FA and multiplexer, we have reduced power and delay of 8-bit ALU as compare to existing design. All design weresimulated using DSCH and Microwind 3.5 in 65 nm BSIM4 technology. Performance analyses were done with respect to power, delay and power delay product.