{"title":"Performance Analysis of Secure Hash Algorithm-2 (SHA-) and Implementing on FPGA","authors":"Jyoti Patil Devaji, N. Iyer, Rajeshwari Mattimani","doi":"10.1007/978-981-16-4177-0_1","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":277476,"journal":{"name":"ICT with Intelligent Applications","volume":"51 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICT with Intelligent Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1007/978-981-16-4177-0_1","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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