An FPGA-Based Data Receiver for Digital IC Testing

Wei-Chen Huang, G. Hou, Jiun-Lang Huang, Terry Kuo
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引用次数: 3

Abstract

FPGA-based digital IC test equipment is a promising solution for low to mid-end applications. In the past, several FPGA data/timing formatters have been demonstrated to generate test waveforms at 100 MHz symbol rate and 200 ps or better resolution. In this paper, an FPGA-based test response receiver for digital IC testing is proposed. First, a three-stage round-trip-delay compensation scheme is introduced so that the strobe window can fully cover the test response window. Then, the corresponding characterization and calibration techniques are developed for the programmable delay line and roundtrip-delay. A prototype receiver is implemented on a Xilinx Spartan 6 FPGA; measurement results show that it is capable of 100 MHz sampling rate with 200 ps strobe position resolution.
一种基于fpga的数字集成电路测试数据接收器
基于fpga的数字集成电路测试设备是一种很有前途的中低端应用解决方案。在过去,几个FPGA数据/时序格式化器已经被证明可以在100 MHz符号速率和200 ps或更好的分辨率下生成测试波形。提出了一种基于fpga的数字集成电路测试响应接收机。首先,提出了一种三级往返时延补偿方案,使频闪窗口能够完全覆盖测试响应窗口。然后,开发了相应的可编程延迟线和往返延迟的表征和校准技术。在Xilinx Spartan 6 FPGA上实现了原型接收器;测量结果表明,该系统具有100mhz的采样率和200ps的频闪位置分辨率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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