Effects of critically damped total PDN impedance in chip-package-board co-design

Abstract

As CMOS LSIs operate at higher clock frequency and at lower supply voltage, power integrity is becoming a critical issue to maintain digital electronic systems more stable. Power supply fluctuation excited by core circuits or I/O circuits induces logic instability and electromagnetic radiation. Therefore, total impedance of power distribution network (PDN) must be taking into consideration in the chip-package-board co-design. Especially, anti-resonance peaks in the PDN due to the parallel combination of on-chip capacitance and package inductance induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by designing different on-chip PDN properties. The measured power supply noises for the four test chips successfully showed typical characteristics of 3 different regions. The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on a chip.