Optimization of equalization architecture for the high-speed serial communication

Abstract

This paper investigates the optimization of equalization architecture for the high-speed serial communication, especially for 25Gbps or above backplane communication. By using the ADS Channel Simulator and taking advantage of the frequency and impulse responses, the high speed backplane channel is analyzed at first. Then various equalization architectures including the high frequency boost values of linear equalizer (LE) and tap coefficients of decision feedback equalizer (DFE) are analyzed in detail. It is shown that much better performance can be obtained by using some combined LE/DFE compared to using LE or DFE separately, and the cost is only a little increase in complexity.