J. D. Bolanos-Jojoa, J. M. Espinosa-Duran, Jaime Velasco-Medina
{"title":"Efficient hardware design of Forward and Inverse Walsh-Hadamard transform","authors":"J. D. Bolanos-Jojoa, J. M. Espinosa-Duran, Jaime Velasco-Medina","doi":"10.1109/STSIVA.2014.7010174","DOIUrl":null,"url":null,"abstract":"This work presents two efficient hardware implementations of Forward and Inverse 2D-Walsh-Hadamard Transforms that do not use memory for the transposition operation. The first one is based on wired-transposition and the second one does not require transposition. In the last case, we designed a large 1D-WHT in order to obtain a 2D transform. The architectures were completely described in VHDL and they are flexible and parameterizable from the viewpoint of the number of inputs (N) and the number of bits of each input (n). The results show that the proposed designs have a very high throughput which makes them very suitable for several image and video processing applications and embedded systems based on H.264.","PeriodicalId":114554,"journal":{"name":"2014 XIX Symposium on Image, Signal Processing and Artificial Vision","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 XIX Symposium on Image, Signal Processing and Artificial Vision","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/STSIVA.2014.7010174","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This work presents two efficient hardware implementations of Forward and Inverse 2D-Walsh-Hadamard Transforms that do not use memory for the transposition operation. The first one is based on wired-transposition and the second one does not require transposition. In the last case, we designed a large 1D-WHT in order to obtain a 2D transform. The architectures were completely described in VHDL and they are flexible and parameterizable from the viewpoint of the number of inputs (N) and the number of bits of each input (n). The results show that the proposed designs have a very high throughput which makes them very suitable for several image and video processing applications and embedded systems based on H.264.