Resolution of Customer Return Non-Volatile Memory Data Retention Bit Failures through Bit Map Verification and Bit Cell Characterization by Nanoprobe Analysis
{"title":"Resolution of Customer Return Non-Volatile Memory Data Retention Bit Failures through Bit Map Verification and Bit Cell Characterization by Nanoprobe Analysis","authors":"Randal E. Mulder","doi":"10.31399/asm.cp.istfa2021p0224","DOIUrl":null,"url":null,"abstract":"\n A major customer had been returning devices for nonvolatile memory (NVM) data retention bit failures. The ppm level was low but the continued fallout at the customer location was causing a quality and reliability concern. The customer wanted a resolution as to the cause of the failures and for a corrective action.\n An NVM bit data retention failure occurs when a programmed bit loses it programmed data state over time and flips to the opposite data state (0 -> 1 or 1 -> 0) causing a programming error. Previous failure analysis results on several failing devices with a single NVM bit data retention failure was inconclusive. TEM analysis showed no difference between the failing bit and neighboring passing bit. The lack of results led to the questioning of the accuracy of the bit map documentation and if the TEM analysis was being performed at the correct bit location. Bit map documentation takes the failing bit's electrical address and converts it to a physical address location. If the bit map documentation is incorrect, locating the failing bit is not possible and physical failure analysis will not be performed at the correct bit location.\n This paper will demonstrate how Atomic Force Probe (AFP) nanoprobe analysis was used to first verify the bit map documentation by determining the programming of bits at specific locations through bit cell characterization; and then characterize the failing bit location to verify the programming error and determine the possible failure mechanism based on its electrical signature followed by the appropriate physical analysis to determine the failure mechanism.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"59 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.31399/asm.cp.istfa2021p0224","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A major customer had been returning devices for nonvolatile memory (NVM) data retention bit failures. The ppm level was low but the continued fallout at the customer location was causing a quality and reliability concern. The customer wanted a resolution as to the cause of the failures and for a corrective action.
An NVM bit data retention failure occurs when a programmed bit loses it programmed data state over time and flips to the opposite data state (0 -> 1 or 1 -> 0) causing a programming error. Previous failure analysis results on several failing devices with a single NVM bit data retention failure was inconclusive. TEM analysis showed no difference between the failing bit and neighboring passing bit. The lack of results led to the questioning of the accuracy of the bit map documentation and if the TEM analysis was being performed at the correct bit location. Bit map documentation takes the failing bit's electrical address and converts it to a physical address location. If the bit map documentation is incorrect, locating the failing bit is not possible and physical failure analysis will not be performed at the correct bit location.
This paper will demonstrate how Atomic Force Probe (AFP) nanoprobe analysis was used to first verify the bit map documentation by determining the programming of bits at specific locations through bit cell characterization; and then characterize the failing bit location to verify the programming error and determine the possible failure mechanism based on its electrical signature followed by the appropriate physical analysis to determine the failure mechanism.