The Experimental Circuits of D-Mode GaAs pHEMT Serial-to-Parallel Converter Blocks

Abstract

An active electronically scanned array is now in widespread commercial use, e.g., in 5G massive MIMO, or automotive radar. Each antenna in an array has its transmit-receive module (TRM). A control system is in charge of the amplitude and phase of each TRM. To simplify the control system, TRM may have an onboard logic circuit. Such a solution may reduce the overall system dimensions even for the GaAs process having a large size of logic gates. A serial to parallel converter (SPC) is typically an integrated logic block in TRM. The SPC converts serial to parallel data and performs the required voltage translation. Usually, E/D-mode GaAs technology is used for logic circuit implementation. However, the D-mode-only GaAs process is less expensive. The search for a way to improve the D-mode-only GaAs logic circuit performance is continuing. The experimental samples of D-mode-only GaAs pHEMT SPC blocks are presented. The measurement results showed the correct operation of the NOT gate and input voltage translator. These blocks’ power consumption is 2.5 mW and 7.5 mW, respectively. The 4-bit shift register was designed using the proposed NOT gate. The measurement results showed the correct operation of the shift register at 60 kHz. Estimated power consumption except output buffer is 26.8 mW/bit which is comparable to the best reported D-mode-only SPC.