Different I/O standard based Wi-Fi enable 32-bit ALU design on 90nm FPGA

Abstract

In this paper, we have tried to make energy efficient ALU on 90nm based Virtex-4 FPGA using different I/O standards, as with the scaling of technology power dissipation has become a major concern for high performance ALU design. As 50% of the total power of ALU is dissipated only in clock and I/O pads, hence in order to make it energy efficient clock gating technique is introduced and the analysis of power dissipation has taken on different I/O standards. It is Wi-Fi enable because we are operating our ALU on frequencies of different IEEE. We are analyzing the value of power dissipation using different I/O standards and on different Wi-Fi channel frequencies. We are achieving reduction in total power dissipation to 95.13% with LVCMOS15 and 95.18% with LVDCI_15 and after introducing Clock Gating we are achieving reduction in total power dissipation to 95.35% with LVCMOS_15 and 94.99% with LVDCI_15.