A 250—800-MHz Multiplying DLL for Reference Frequency Generation with Improved Phase Noise

Abstract

A programmable multiplying delay-locked loop (MDLL) with two operating modes which utilize different closedloop transfer functions is presented. The MDLL output frequency is adjustable in the range from 250 to 800 MHz, with fixed input reference of 50 MHz and multiplication factor within 5 –16. The influence of MDLL’s transfer function change on the phase noise (PN) and reference spur performances was investigated. In the first mode, the voltage-controlled oscillator’s (VCO’s) output signal is fed directly to the phase-frequency detector (PFD). By contrast, the frequency of the output signal in the second mode is first divided and then fed to the PFD input. The pros and cons of both modes are discussed alongside with possible improvements. The MDLL is designed in a commercially available 130-nm BiCMOS process technology. At 800-MHz carrier frequency, the MDLL achieves PN of -114.87 and -127.68 dBc/Hz at 10-kHz and 1-MHz offset frequencies, respectively.