Efficient carry generation technique incorporating energy recovering logic circuitry for low power VLSI

Abstract

Dynamic power consumption is a major concern for designing various modern age information systems and computers. Advances in low power VLSI design results in charge recovery based adiabatic logic concept, which proves to be a potential parametric to design CMOS circuits for various low power applications. Research in this domain is fueled by the fact that instead of discharging the load capacitance to ground, the charge flows back to power supply and can be reused. Keeping the advantages of energy recovery logic in mind, we demonstrate low energy carry break logic exploiting certain aspects of carry generation based on the bit positions in input vectors. Design has been implemented in 90 nm TSMC process, showing 70% improvement in power.