{"title":"CAD automation module based on cell moving algorithm for ECO timing optimization","authors":"Kan Mei War, B. A. Rosdi, C. Wee","doi":"10.1109/ISIEA.2011.6108716","DOIUrl":null,"url":null,"abstract":"Incremental placement or Engineering Change Order (ECO) placement remains one of the most influential steps in Very Large Scale Integration (VLSI) layout design. New logic may be added into design after placement stage to meet functionality requirement. The added logic will cause design timing to become worse. In this paper, we develop an incremental placement Computer Aided Design (CAD) automation module to improve timing of the layout design. This incremental placement serves as a post-placement optimization solution that provide a cells position adjustment strategy such that no cells overlap occur and ensure no significant deviation from initial placement. Experiment is carried out by integrating the developed CAD automation module with standard industrial Electronic Design Automation (EDA) and Intel in-house design tools. Experimental results show that our approach can effectively reduce maximum and total negative slack on most of the benchmark circuits.","PeriodicalId":110449,"journal":{"name":"2011 IEEE Symposium on Industrial Electronics and Applications","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE Symposium on Industrial Electronics and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISIEA.2011.6108716","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Incremental placement or Engineering Change Order (ECO) placement remains one of the most influential steps in Very Large Scale Integration (VLSI) layout design. New logic may be added into design after placement stage to meet functionality requirement. The added logic will cause design timing to become worse. In this paper, we develop an incremental placement Computer Aided Design (CAD) automation module to improve timing of the layout design. This incremental placement serves as a post-placement optimization solution that provide a cells position adjustment strategy such that no cells overlap occur and ensure no significant deviation from initial placement. Experiment is carried out by integrating the developed CAD automation module with standard industrial Electronic Design Automation (EDA) and Intel in-house design tools. Experimental results show that our approach can effectively reduce maximum and total negative slack on most of the benchmark circuits.