Efficient and universal method to design multiple field limiting rings for power devices

Abstract

For the first time, an efficient and universal method to design multiple field limiting rings (FLR) structure, which applicable to power devices with thin drift layer is proposed. Avalanche breakdown simulations of simplified structures are performed in each three area; the near main junction area, the outmost area, and the other. From simulation results, optimal spacing between each neighboring FLR is efficiently extracted. Phenomena related breakdown voltage determination in each area are also clarified. We demonstrate that the edge termination structures designed along our guidelines succeed to obtain the target blocking voltage in different 600 V class processes.