Design and synthesis of bandwidth efficient QPSK modulator for low power VLSI design

A. Khanna, Anju Jaiswal, Harsh Jain
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引用次数: 3

Abstract

In recent years digital designs have been highly automated, and the digital modulation provides more information capacity, compatibility, higher data security, better quality communications and quicker system availability with digital services. This paper proposes a QPSK module based on π/4 modulation technique. A simulative investigation on the bandwidth efficiency of the QPSK modulator has been implemented with the proposed technique; and thereby compared with the conventional BPSK modulation scheme. Synthesis and implementation of QPSK modulation technique is described viz. subsystem modules of digital communication. The QPSK modulator unit will be modelled using HDL code and simulation is done using Modelsim 10.d simulator followed by synthesis and FPGA implementation of the design using Xilinx ISE design suite using Spartan-6 FPGA kit.
用于低功耗VLSI设计的带宽高效QPSK调制器的设计与合成
近年来,数字设计已经高度自动化,数字调制提供了更多的信息容量,兼容性,更高的数据安全性,更好的通信质量和更快的系统可用性与数字服务。提出了一种基于π/4调制技术的QPSK模块。利用该技术对QPSK调制器的带宽效率进行了仿真研究;从而与传统的BPSK调制方案进行比较。介绍了QPSK调制技术的综合与实现,即数字通信子系统模块。QPSK调制器单元将使用HDL代码进行建模,并使用Modelsim 10进行仿真。d模拟器随后进行合成和FPGA实现,设计采用赛灵思ISE设计套件,采用Spartan-6 FPGA套件。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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