{"title":"Reconfigurable Hardware Implementation of Arithmetic Modulo Minimal Redundancy Cyclotomic Primes for ECC","authors":"Brian Baldwin, W. Marnane, R. Granger","doi":"10.1109/ReConFig.2009.67","DOIUrl":null,"url":null,"abstract":"The dominant cost in Elliptic Curve Cryptography (ECC) over prime fields is modular multiplication. Minimal Redundancy Cyclotomic Primes (MRCPs) were recently introduced by Granger~\\ea for use as base field moduli in ECC, since they permit a novel and very efficient modular multiplication algorithm. Here we consider a reconfigurable hardware implementation of arithmetic modulo a $258$-bit example, for use at the $128$-bit AES security level. We examine this implementation for speed and area using parallelisation methods and inbuilt FPGA resources. The results are compared against a current method in use, the Montgomery multiplier.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Conference on Reconfigurable Computing and FPGAs","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ReConFig.2009.67","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
The dominant cost in Elliptic Curve Cryptography (ECC) over prime fields is modular multiplication. Minimal Redundancy Cyclotomic Primes (MRCPs) were recently introduced by Granger~\ea for use as base field moduli in ECC, since they permit a novel and very efficient modular multiplication algorithm. Here we consider a reconfigurable hardware implementation of arithmetic modulo a $258$-bit example, for use at the $128$-bit AES security level. We examine this implementation for speed and area using parallelisation methods and inbuilt FPGA resources. The results are compared against a current method in use, the Montgomery multiplier.