Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAs

Abstract

In this paper we present the post-processing algorithm, cut substitution, for technology mapping for LUT-based FPGAs to minimize the area under depth minimum constraint. The problem to generate a LUT's network whose area is minimum under depth minimum constraint seems to be as difficult as NP-hard class problem. Cut substitution is the process to generate a local optimum solution by eliminating redundant LUTs while the depth of network is maintained. The experiments shows that the proposed method derives the solutions whose area are 9% smaller than the solutions of a previous state-of-the-art, DAOmap on average.