Configurable Hardware Architecture of Multidimensional Convolution Coprocessor

Geranun Boonyuu, Sumek Wisayataksin
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引用次数: 1

Abstract

We propose a configurable coprocessor for the convolutional neural network (CNN) that suit various models of CNN. It can operate 2D standard convolution, 2D depthwise separable convolution, 3D convolution, and a fully connected layer. The proposed processing cluster consists of 72 processing units (PUs) of half-precision floating-point to assist the main processor in embedded systems. The experimental results on Artix-7 FPGA revealed that our design has 12.16 GOPs per cluster. Moreover, this architecture was designed to be scalable for the systems with higher performance.
多维卷积协处理器的可配置硬件结构
本文提出了一种可配置的卷积神经网络协处理器,适用于不同的卷积神经网络模型。它可以进行二维标准卷积、二维深度可分离卷积、三维卷积和全连通层。所提出的处理集群由72个半精度浮点处理单元组成,以辅助嵌入式系统中的主处理器。在Artix-7 FPGA上的实验结果表明,我们的设计每个集群具有12.16个GOPs。此外,该体系结构被设计为具有更高性能的系统的可扩展性。
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