AAG: An automatic assertion generation framework for RTL designs

Abstract

Assertion Based Verification (ABV) has been shown to be a very effective functional verification approach for digital designs. ABV is usually employed by the verification engineers by embedding assertions in the hardware description language (HDL) code manually by studying the design and user provided specifications. However, with the growing complexity of digital systems, understanding different designs and specifications in general and then writing assertions manually in particular has become quite tedious. In this paper, we propose to alleviate these issues by proposing AAG, i.e., an Automatic Assertion Generation framework that accepts the Register Transfer Level (RTL) code in Verilog, generates the corresponding randomized testbench automatically and then generates the corresponding value change dump (VCD) file from the simulation of RTL code using the generated testbench. In the proposed verification framework, we use GoldMine as an assertion generation engine. The paper also explains, with help of case studies, how can verification engineers benefit from AAG.