Design and modeling for chip-to-chip communication at 20 Gbps

Abstract

This paper presents the design of serial chip-to-chip communication at 20 Gbps including modeling and correlation for PCBs (Printed Circuit Boards) with FR4 substrate materials. The entire channel under investigation includes two packages, a 21-layer ceramic and a 12-layer organic, and a 22-layer PCB. A probing station, microprobes and a VNA are used to measure the entire channel S-parameters and the measurement is correlated to the simulation up to 20 GHz. Extended study for the channel with low loss PCB substrate material is simulated. Time-domain eye comparisons for the FR4 channel, low loss channel, and the FR4 channel with equalization are given. A general design rule as well as new technologies for the high-speed channel design at 20 Gbps and beyond are discussed and given in the conclusion.