RISC approach to design of fuzzy processor architecture

Abstract

An attempt is made to design a fuzzy information processor as an application-specific processor using a quantitative approach. The approach was developed by reduced instruction set computer (RISC) architecture designers. The basic architecture proposed consists of a RISC as a core processor with special hardware functional units for fuzzy-logic-related operations. Fuzzy-related functional units should be either integrated into a core or placed as a coprocessor. In particular, the following two issues are considered: an instruction set for fuzzy information processing; and vector instruction for fuzzy theoretic operations.<>