Systematic design of an ideal toolflow for accelerating big data applications on FPGA platforms

Abstract

The tremendous explosion of data has led to the “big data challenge” in the various domains of the current digital age including financial analytics, weather forecasting and bioinformatics. The processing requirements of the voluminous and complex data sets produced by the current data explosion are outpacing the computational capacity of traditional hardware platforms and thus necessitating adoption of high performance computing architectures such as clusters, cloud computing and customisable processing hardware such as field programmable gate arrays. In particular, FPGAs offer excellent flexibility, massive parallel computational capacity and good power efficiency which can meet the high processing demands of big data applications. However, despite their excellent processing merits, FPGAs are still suffering from low adoption by designers. Standard FPGA languages and tools are difficult and exclusive to users with digital hardware design expertise. Multiple high-level languages and design flows targeted at different application domains have been developed to meet the FPGA design challenge. However, there is a lack of a standardised specification that defines clearly how a high-level FPGA design flow should be and what it should be capable of. This paper employs a system engineering approach to design and prototype an ideal high-level FPGA design Toolflow for the computational finance domain which utilises a simple standard software programming language to program the FPGA. The detailed specification of the ideal high-level FPGA Toolflow is presented and discussed. Preliminary results between a purely software design in comparison to a hardware design generated using the prototyped high-level FPGA Toolflow are presented.