Parallel placement on reduced array architecture

Abstract

The authors present a hardware accelerator for a module placement algorithm based on the divide-and-conquer paradigm. They consider a partitioning algorithm for the approximate solution of a large placement problem. This algorithm divides the set of logic modules into small clusters and generates an optimal placement for each cluster. Finally, in a pasting step, the algorithm combines the optimal solutions for the smaller problems into a near-optimal solution for the original placement problem. The algorithm lends itself very naturally to a parallel realization, and maps nicely onto an SIMD (single-instruction, multiple data-stream) organization. Considerations such as cost-effectiveness and suitability to VLSI implementation led to the selection of the reduced array architecture as the target architecture for the placement accelerator.<>