RTL to GDSII of Harvard Structure RISC Processor

H. V. Ravish Aradhya, Gopal Kanase, V. Y
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引用次数: 1

Abstract

This paper speaks about design of RISC processor and its implementation from RTL to GDSII. Verification of RISC processor Harvard structure is carried using Verilog (RTL file) and test bench for that Verilog file. Cadence NC Launch tool is used for simulation of code. Later verified Verilog file along with. sdc and .lib files, gate level net list was generated from cadence Genus tool. Till this part of gate level net list generations front end part of design will be carried out. Output of Genus tool are verified gate level net list file and. sdc constraints file. Pre-layout simulation results for power, area and timing are carried out. In backend design, cadence Innovus tool was used for floor planning, power planning and routing. Here also post layout simulations carried for power, timing and area. All these processes are carried out using 180nm technology cadence tool. The physical implementation of Harvard Structure RISC Processor is successfully implemented on Cadence Innovus tool. After carrying out pre-clock tree synthesis, post clock tree synthesis and post routing of circuit, one has obtained optimized results for timing 9.236ps, power 0.53155682W and area 17067.7584µm2.
哈佛结构RISC处理器GDSII的RTL
本文论述了RISC处理器的设计及其从RTL到GDSII的实现。利用Verilog (RTL文件)和Verilog文件的测试台对RISC处理器Harvard结构进行验证。Cadence NC启动工具是用来进行仿真的代码。后来验证的Verilog文件一起。sdc和.lib文件,门级网列表是由节奏属工具生成的。直到这一部分的门级网表生成前端部分的设计才会进行。属工具的输出是验证门级网表文件和。SDC约束文件。给出了功率、面积和时序的预布局仿真结果。在后台设计中,采用cadence Innovus工具进行平面规划、电源规划和布线。这里也张贴布局模拟进行功率,时间和面积。所有这些工艺都采用180nm技术的节奏工具进行。在Cadence Innovus工具上成功实现了哈佛结构RISC处理器的物理实现。通过对电路进行时钟树前合成、时钟树后合成和电路后布线,得到了时序9.236ps、功率0.53155682W、面积17067.7584µm2的优化结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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