A new synthesis efficient, high density and high speed ORCA FPGA

Abstract

This paper describes a new ORCA FPGA that focuses on enhancing the speed and gate density of logic systems implemented using high-level logic synthesis. The new family called ORCA 3C/3T, follows the successful ORCA families: 1C, 2C, 2CA and 2TA. The architecture has been designed for efficiently implementing behavioral-level "functions", in addition to regular digital "logic". It includes Look-Up Tables (LUTs), Flip-Flops (FFs) and a PAL-type decoder block grouped in a twin-nibble fashion. The programmable interconnections are designed to provide fast hierarchical connections. To meet the challenge of implementing larger systems, the architecture supports system-level features such as a Programmable Clock Manager (PCM) and a microprocessor interface that can be used during and after the configuration.