A Novel Mini-LVDS Receiver in 0.35-um CMOS

Abstract

This paper presents the design of receiver circuits for flat-plane application. Due to the differential transmission technique and the low voltage swing, mini-LVDS (low-voltage differential signaling) allows high transmission speeds and low power consumption at the same time. In the proposed receiver, high transmission speed with the minimum common-mode and differential voltage at the input for mini-LVDS application was achieved. The circuit was designed in a 3.3-V 0.35- mum CMOS technology, and the transmission operations is more than 500 Mb/s with random data patterns. The total power consumption is 3.5 mW.