Enhanced stacked-FETs SOI-CMOS switch biasing strategy for high power applications

Abstract

Power handling capability is the most rigorous specification in the design of a high-power RF switch. The stacked-FETs technique is a common method to increase the handling power. However, the conventional stacked-FETs structure has a critical issue that is the severe imbalanced voltage division across the FET stacks degrading the power handling capability and linearity in the presence of a large input power level. To further improve the power handling capability, we propose an enhanced switch biasing strategy to achieve even voltage distribution among the stacked FETs. Based on the new method, a stacked-FETs single-pole four-throw (SP4T) antenna switch in a 130nm silicon-on-insulator (SOI) CMOS process for high-power applications is devised as an experimental vehicle. The experimental results demonstrate that the proposed switch adopting the new biasing strategy reveals higher power handling capability and lower harmonic distortion compared to the conventional version, which is suitable for GSM-based and antenna tuning applications.