{"title":"A 216 nW/channel DSP engine for triggering theta phase-locked brain stimulation","authors":"Ahmed Alzuhair, D. Markovic","doi":"10.1109/BIOCAS.2017.8325189","DOIUrl":null,"url":null,"abstract":"We present an algorithm and, for the first time, a chip to predict the neural theta oscillation phase, for closed-loop phase-locked stimulation triggering. The performance, assessed on test data recorded from human hippocampus, achieves high precision and accuracy in targeting any theta phase with 25%, 50%, and 75% of the predictions falling within ±13, ±28, and ±53 degrees from the desired target phase, respectively. Design interleaving channel-depth optimization achieves 41% energy and 58% area savings compared to a single-channel design. The 32-channel chip consumes a 216 nW per channel and occupies a core area of 0.011 mm2 per channel in a 40nm low-power technology, making it suitable for implantable devices.","PeriodicalId":361477,"journal":{"name":"2017 IEEE Biomedical Circuits and Systems Conference (BioCAS)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE Biomedical Circuits and Systems Conference (BioCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIOCAS.2017.8325189","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
We present an algorithm and, for the first time, a chip to predict the neural theta oscillation phase, for closed-loop phase-locked stimulation triggering. The performance, assessed on test data recorded from human hippocampus, achieves high precision and accuracy in targeting any theta phase with 25%, 50%, and 75% of the predictions falling within ±13, ±28, and ±53 degrees from the desired target phase, respectively. Design interleaving channel-depth optimization achieves 41% energy and 58% area savings compared to a single-channel design. The 32-channel chip consumes a 216 nW per channel and occupies a core area of 0.011 mm2 per channel in a 40nm low-power technology, making it suitable for implantable devices.